// module name: ALU 
// author: yangtao2019
// date: 2021.07.10

`timescale 1ns / 1ps

module ALU(
    input[3:0] alu_ctl,
    input[63:0] num1, num2,
    output[63:0] num_out,
    output ZeroSign
);

    // true table see P175
    assign num_out =   ((alu_ctl==4'b0000)? num1 & num2 :
                        (alu_ctl==4'b0001)? num1 | num2 :
                        (alu_ctl==4'b0010)? num1 + num2 :
                        (alu_ctl==4'b0110)? num1 - num2 :
                        (alu_ctl==4'b1111)? num1 + num2<<12:
                                64'h0000_0000_0000_0000);

    assign ZeroSign = (num_out==64'b0);

endmodule
